Add test

3 files changed, 46 insertions, 4 deletions

diff --git a/MicSim/components/caretaker.py b/MicSim/components/caretaker.py
index 6153350..82ac63d 100644
--- a/MicSim/components/caretaker.py
+++ b/MicSim/components/caretaker.py
@@ -15,7 +15,7 @@ class Caretaker:
 		if key=="MBRU": # If we ask for unsigned
 			return(abs(self.objects["MBR"]))
 		elif key== "MBR":
-			if (self.objects[key]>>7)==1: # If it a negative number (2 complement)
+			if abs(self.objects[key]>>7)==1: # If it a negative number (2 complement)
 				return(-((self.objects[key]-1)^0xFF)) # transforme bin negative number to python negative number
 			else:
 				return(self.objects[key])
diff --git a/MicSim/test/test_caretaker.py b/MicSim/test/test_caretaker.py
new file mode 100644
index 0000000..5cc7483
--- /dev/null
+++ b/MicSim/test/test_caretaker.py
@@ -0,0 +1,45 @@
+#!/usr/bin/python
+
+from components.caretaker import Caretaker
+import unittest
+from random import randint
+
+class CaretakerTest(unittest.TestCase):
+	
+	def setUp(self):
+		"""
+			Init test
+		"""
+		self.c=Caretaker(1000)
+	
+	def test___getitem__(self):
+		"""
+			Test if getitem operation follow Mic-1 rules
+		"""
+		toWrite=randint(0,126) # Only 7 bit for signed MBR (2^7=127)
+		self.c["MBR"]=-toWrite
+		self.assertEqual(self.c["MBRU"],toWrite,"Tested with {}".format(-toWrite))
+		self.assertEqual(self.c["MBR"],-(-((toWrite-1)^0xFF)),"Tested with {}".format(-toWrite))
+		self.c["MBR"]=toWrite
+		self.assertEqual(self.c["MBRU"],toWrite,"Tested with {}".format(toWrite))
+		self.assertEqual(self.c["MBR"],toWrite,"Tested with {}".format(toWrite))
+
+		with self.assertRaises(KeyError): # Check it returns a KeyError
+			self.c["kjhkjhkoih"+str(randint(0,7698))]
+			
+	def test___setitem__(self):
+		"""
+			Test if getitem operation follow Mic-1 rules
+		"""
+		try:
+			self.c["RAM"]="Test"
+		except Exception:
+			self.fail("Failed to assign RAM to caretaker")
+
+
+
+
+
+
+if __name__ == "__main__":
+	unittest.main()
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py
index 58e42cb..6baf158 100644
--- a/MicSim/test/test_ram.py
+++ b/MicSim/test/test_ram.py
@@ -97,8 +97,5 @@ class RamTest(unittest.TestCase):
 			self.caretaker["PC"]=-1*randint(0,self.ramSize-1)
 			ram.fetch()
 		
-		
-		
-
 if __name__ == "__main__":
 	unittest.main()