Clean code

4 files changed, 18 insertions, 22 deletions

diff --git a/MicSim/components/caretaker.py b/MicSim/components/caretaker.py
index ab20fba..6153350 100644
--- a/MicSim/components/caretaker.py
+++ b/MicSim/components/caretaker.py
@@ -1,13 +1,15 @@
 #!/usr/bin/python
 
+from components.ram import Ram
+
 class Caretaker:
 	
-	def __init__(self):
+	def __init__(self,ramSize):
 		self.objects=dict() # Create empty objects pool
 		# Add registers to pool
 		for reg in ["MAR","MDR", "PC", "MBR", "SP","LV","CPP","TOS","OPC","H"]:
 			self.objects[reg]=0
-		self.objects["RAM"]=None
+		self.objects["RAM"]=Ram(self,ramSize)
 	
 	def __getitem__(self,key):
 		if key=="MBRU": # If we ask for unsigned
diff --git a/MicSim/components/microprogram.py b/MicSim/components/microprogram.py
index c2a3552..12f38e4 100644
--- a/MicSim/components/microprogram.py
+++ b/MicSim/components/microprogram.py
@@ -8,13 +8,14 @@ class Microprogram:
 		if self.c["RAM"]==None: # Check if RAM is initialize
 			raise RuntimeError("Microprogram initialization fail, RAM is not initialized")
 	
-	def run(self):
+	def run(self,constantPoolLocation, stackLocation):
 		"""
 			Start microprogram
 		"""
-		self.c["LV"]=(1024)# Place stack to 1024
-		self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
-		
+		self.c["LV"]=stackLocation# Place stack to 1024
+		self.c["SP"]=stackLocation-1 # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
+		self.c["CPP"]=constantPoolLocation
+
 		for i in range(1,30): # Launche first 30 insctructions
 			self.fetch() # Fetch
 			self.c["PC"]+=1 # INC PC after fetch
@@ -202,6 +203,7 @@ class Microprogram:
 		self.c["H"]=self.c["MBRU"]|self.c["H"]
 		self.c["PC"]=self.c["OPC"]+self.c["H"]
 		##################
+		
 	def F(self): # This function is here just to follow ijvm implementation of "Structured Computer Organization"
 		self.fetch();self.c["PC"]+=1 # Needed because memory access take 1 cycle in simulation
 		self.c["PC"]=self.c["PC"]+1
diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py
index 59de862..2d0628e 100644
--- a/MicSim/components/ram.py
+++ b/MicSim/components/ram.py
@@ -11,13 +11,13 @@ class Ram:
 		"""
 			Load a Ram file into self.data
 		"""
-		data=dict()
-		addr=0
+		self.data=dict()
 		f=open(filepath,"r")
+		addr=0
 		for line in f.readlines():
 			line=line.rstrip() # remove \n
 			if line in ijvm:
-				data[addr]=int(ijvm[line])
+				self.data[addr]=int(ijvm[line])
 			else:
 				try:
 					value=int(line,0)
@@ -25,11 +25,10 @@ class Ram:
 					raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line))
 				if value>255:
 					raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr)) 
-				data[addr]=value
+				self.data[addr]=value
 			addr+=1
 		f.close()
-		self.data=data
-	
+		
 	def write(self):
 		"""
 			Write data to memory based Mic-1 architecture
diff --git a/MicSim/micsim.py b/MicSim/micsim.py
index a45311f..c4cb6c3 100755
--- a/MicSim/micsim.py
+++ b/MicSim/micsim.py
@@ -4,15 +4,8 @@ from components.microprogram import Microprogram
 from components.ram import Ram
 from components.caretaker import Caretaker
 
-c=Caretaker() 					# Init components
-RAM=Ram(c,5000) 				# Init ram
-RAM.loadRamFile("./ram.txt")	# Load Ram from file
-c["RAM"]=RAM 					# Add ram to components
-
+c=Caretaker(5000) 					# Init components (stackLocation)
+c["RAM"].loadRamFile("./ram.txt")	# Load Ram from file
 
 mic=Microprogram(c) 			# Create micro program
-mic.run() 						# Run the micro program
-
-mic.rd()
-print(bin(c["MDR"]))
-print(RAM.dump())
+mic.run(800, 1024) 				# Run the micro program with run(constantPoolLocation,stackLocation)