Clean code and add extras instructions

4 files changed, 46 insertions, 10 deletions

diff --git a/components/ijvm.py b/components/ijvm.py
index b8ca8a2..97fb6bd 100644
--- a/components/ijvm.py
+++ b/components/ijvm.py
@@ -22,3 +22,7 @@ ijvm=dict({
 	"SWAP":0x5F,
 	"WIDE":0xC4
 })
+
+# Add extras instructions
+ijvm["OUT"]=0x23 # Print next byte as char
+ijvm["HALT"]=0x2F # Stop simulator
diff --git a/components/microprogram.py b/components/microprogram.py
index f415fcf..943e502 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -4,31 +4,47 @@ from components.ijvm import ijvm
 class Microprogram:
 	
 	def __init__(self,components):
-		self.c=components
-		if self.c["RAM"]==None:
+		self.c=components # Link components to microprogram
+		if self.c["RAM"]==None: # Check if RAM is initialize
 			raise RuntimeError("Microprogram initialization fail, RAM is not initialized")
 	
 	def run(self):
+		"""
+			Start microprogram
+		"""
 		self.c["LV"]=(1024)# Place stack to 1024
 		self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
 		
 		for i in range(1,30): # Launche first 30 insctructions
 			self.fetch() # Fetch
-			self.c["PC"]+=1 # INC PC
-			self.exec() # Execute opcode
+			self.c["PC"]+=1 # INC PC after fetch
+			if self.exec()==1: # Execute opcode and halt if return code is 1
+				break;
 			
 	def fetch(self):
+		"""
+			Fetch next byte from memory into MBR
+		"""
 		opcode=self.c["RAM"].fetch()
 		self.c["MBR"]=opcode # Opcode to MBR
 		
 	def rd(self):
+		"""
+			Read data into memory
+		"""
 		data=self.c["RAM"].read()
 		self.c["MDR"]=data
 		
 	def wr(self):
+		"""
+			Write data into memory
+		"""
 		self.c["RAM"].write()
 
 	def exec(self):# link: https://users-cs.au.dk/bouvin/dComArk/2015/noter/Note_2/#Instructions
+		"""
+			Execute next opcode
+		"""
 		opcode=self.c["MBR"] # Get loaded OpCode
 		if opcode==ijvm["NOP"]: # NOP
 			pass
@@ -91,13 +107,28 @@ class Microprogram:
 			self.c["MAR"]=self.c["SP"]-1
 			self.wr()
 			self.c["TOS"]=self.c["H"]
+		elif opcode==ijvm["OUT"]:
+			self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
+			print(str(chr(self.c["MBR"])),end="")
+		elif opcode==ijvm["HALT"]:
+			return(1)
 		else:
 			if opcode in ijvm:
 				print("Instruction {} not yet implemented.".format(ijvm[opcode]))
 			else:
 				raise RuntimeError("Instruction {} not found".format(opcode))
+		return(0)
 	
 	def dump(self):
-		print("---------- Stack ----------")
-		self.c["RAM"].dump(self.c["LV"],self.c["SP"])
-		print("---------------------------")
+		"""
+			Print RAM, stack and registers
+		"""
+		print("-------------- RAM --------------")
+		self.c["RAM"].dump()
+		print("------------- Stack -------------")
+		self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"])
+		print("----------- Registers -----------")
+		for key,value in self.c.items():
+			if key!="RAM":
+				print("{}={}".format(key,value))
+		print("---------------------------------")
diff --git a/components/ram.py b/components/ram.py
index c6d05bb..d503929 100644
--- a/components/ram.py
+++ b/components/ram.py
@@ -52,13 +52,11 @@ class Ram:
 		return(value)
 		
 	def dump(self):
-		print("------- RAM --------")
 		for key,value in self.data.items():
 			#print("{}:{}".format(key,bin(value)[2:]))
 			print("{}:{}".format(key,value))
-		print("--------------------")
 		
-	def dump(self,start,end):
+	def dumpRange(self,start,end):
 		for i in range(start,end+1):
 			try:
 				print("{}:{}".format(i,self.data[i]))
diff --git a/ram.txt b/ram.txt
index 5e4ce31..f86ca50 100644
--- a/ram.txt
+++ b/ram.txt
@@ -6,3 +6,6 @@ IADD
 BIPUSH
 10
 POP
+HALT
+OUT
+65