This commit is contained in:
Loic GUEGAN 2018-09-01 17:22:49 +02:00
parent d58349763a
commit 94377da94d
4 changed files with 20 additions and 4 deletions

View file

@ -1,6 +1,9 @@
from components.ijvm import ijvm
# TODO: Switch MAR as 32bits address (multiply its value by for)
# then same for SP and LV
class Microprogram:
def __init__(self,components):