diff --git a/components/caretaker.py b/components/caretaker.py
index 4237702..5707a16 100644
--- a/components/caretaker.py
+++ b/components/caretaker.py
@@ -19,8 +19,15 @@ class Caretaker:
 				return(self.objects[key])
 		return(self.objects[key])
 
-	def __setitem__(self,key,value):# TODO: Do special treatment for MBR (allow only 2^8 value)
-									# TODO: Force data to be at most 32 bits longs (Mic-1 architecture constraint)
+	def __setitem__(self,key,value):
+		if key!="RAM":
+			if value > (2**32) and key!="MBR" and key!="MBRU": # Check value fit in word
+				print("Warning word overflow: value {} on register {}".format(value,key))
+				value=value%(2**32) # Force to fit in word
+			elif value > (2**8) and key=="MBR" and key=="MBRU": # Check value fit in byte
+				print("Warning byte overflow: value {} on register {}".format(value,key))
+				value=value%256 # Force to fit in byte
+
 		self.objects[key]=value
 		
 	def items(self):
diff --git a/components/microprogram.py b/components/microprogram.py
index 4543de1..8ae9703 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -1,6 +1,9 @@
 
 from components.ijvm import ijvm
 
+# TODO: Switch MAR as 32bits address (multiply its value by for)
+#		then same for SP and LV
+
 class Microprogram:
 	
 	def __init__(self,components):
diff --git a/components/ram.py b/components/ram.py
index ddf48d1..b6258e3 100644
--- a/components/ram.py
+++ b/components/ram.py
@@ -19,7 +19,13 @@ class Ram:
 			if line in ijvm:
 				data[addr]=int(ijvm[line])
 			else:
-				data[addr]=int(line,0)
+				try:
+					value=int(line,0)
+				except:
+					raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line))
+				if value>255:
+					raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr)) 
+				data[addr]=value
 			addr+=1
 		f.close()
 		self.data=data
diff --git a/ram.txt b/ram.txt
index 7132b9f..6133f6b 100644
--- a/ram.txt
+++ b/ram.txt
@@ -6,4 +6,4 @@ GOTO
 0
 0
 BIPUSH
-3
+30