This commit is contained in:
Loic GUEGAN 2018-09-01 17:22:49 +02:00
parent d58349763a
commit 94377da94d
4 changed files with 20 additions and 4 deletions

View file

@ -19,8 +19,15 @@ class Caretaker:
return(self.objects[key])
return(self.objects[key])
def __setitem__(self,key,value):# TODO: Do special treatment for MBR (allow only 2^8 value)
# TODO: Force data to be at most 32 bits longs (Mic-1 architecture constraint)
def __setitem__(self,key,value):
if key!="RAM":
if value > (2**32) and key!="MBR" and key!="MBRU": # Check value fit in word
print("Warning word overflow: value {} on register {}".format(value,key))
value=value%(2**32) # Force to fit in word
elif value > (2**8) and key=="MBR" and key=="MBRU": # Check value fit in byte
print("Warning byte overflow: value {} on register {}".format(value,key))
value=value%256 # Force to fit in byte
self.objects[key]=value
def items(self):

View file

@ -1,6 +1,9 @@
from components.ijvm import ijvm
# TODO: Switch MAR as 32bits address (multiply its value by for)
# then same for SP and LV
class Microprogram:
def __init__(self,components):

View file

@ -19,7 +19,13 @@ class Ram:
if line in ijvm:
data[addr]=int(ijvm[line])
else:
data[addr]=int(line,0)
try:
value=int(line,0)
except:
raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line))
if value>255:
raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr))
data[addr]=value
addr+=1
f.close()
self.data=data

View file

@ -6,4 +6,4 @@ GOTO
0
0
BIPUSH
3
30