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Add little endianess, debug memory addressing

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Loic GUEGAN 2018-09-01 19:09:48 +02:00
parent 94377da94d
commit 4a9d274fd7
4 changed files with 16 additions and 18 deletions
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5
components/microprogram.py
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@ -1,9 +1,6 @@
from components.ijvm import ijvm
# TODO: Switch MAR as 32bits address (multiply its value by for)
# then same for SP and LV
class Microprogram:
def __init__(self,components):
@ -164,7 +161,7 @@ class Microprogram:
print("-------------- RAM --------------")
self.c["RAM"].dump()
print("------------- Stack -------------")
self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"])
self.c["RAM"].dumpRange(self.c["LV"]*4,self.c["SP"]*4,4) # Convert address to 32bits value
print("----------- Registers -----------")
for key,value in self.c.items():
if key!="RAM":