.section .crt0, "ax"

// Load data segment to SRAM
	ldr r0, =__data_src__
	ldr r1, =__data_dst__
	ldr r2, =__data_size__
	mov r3, #0
data_seg_start:
	cmp r2, #0
	beq data_seg_end
	ldrb r3, [r0]
	strb r3, [r1]
	add r0, #1
	add r1, #1
	sub r2, #1
	b data_seg_start
data_seg_end:

// Init bss in SRAM
	ldr r0, =__bss_start__
	ldr r1, =__bss_size__
	mov r2, #0
bss_init_start:
	cmp r1, #0
	beq bss_init_end
	strb r2, [r0]
	add r0, #1
	sub r1, #1
	b bss_init_start
bss_init_end:

	// Setup stack
	ldr r0, =SRAM_END
	mov sp, r0

	// Start kernel
	ldr r0, =main
	blx r0

	.set SRAM_END, 0x20042000