70 lines
No EOL
2 KiB
C++
70 lines
No EOL
2 KiB
C++
#include "apic.hpp"
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#include "paging.hpp"
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#include "types.hpp"
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#include "asm.hpp"
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#include "libs/stdio.hpp"
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#define APIC_LAPIC_ADDR 0xFEE00000
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#define APIC_IOAPIC_ADDR 0xFEC00000
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#define APIC_LAPIC_REG_SPURIOUS 0xF0
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#define APIC_LAPIC_TIMER_LVT 0x320
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#define APIC_LAPIC_TIMER_IC 0x380
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#define APIC_LAPIC_TIMER_DVD 0x3E0
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#define APIC_PRIOR 0x80
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#define APIC_DFR 0xE0
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#define APIC_EOI 0xB0
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u8 lapic_space[4096] __attribute__((aligned(4096)));
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u8 ioapic_space[4096] __attribute__((aligned(4096)));
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char enable=0;
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void apic_enable(){
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// Memory Allocation
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PAGE_MAP(lapic_space,APIC_LAPIC_ADDR, PAGING_OPT_PCD|PAGING_OPT_DEFAULTS);
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PAGE_MAP(ioapic_space,APIC_IOAPIC_ADDR,PAGING_OPT_PCD|PAGING_OPT_DEFAULTS);
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// Configure APIC register location and enable it via MSR
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/* u64 lapic_addr=(u64)APIC_LAPIC_ADDR;
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u32 high=lapic_addr>>32;
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u32 low=((u64)APIC_LAPIC_ADDR&0xFFFFFFFF);
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low|=0x800; // Enable apic
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WRITE_MSR(0x1B,high,low);*/
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// Configure LAPIC device using mmap
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apic_write(APIC_LAPIC_REG_SPURIOUS, 0x100&apic_read(APIC_LAPIC_REG_SPURIOUS));
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//apic_write(APIC_DFR, 0xFFFFFFFF);
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// apic_write(APIC_PRIOR, 0);
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apic_write(APIC_LAPIC_TIMER_DVD, 1);
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apic_write(APIC_LAPIC_TIMER_LVT, (1<<17)|61);
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apic_write(APIC_LAPIC_TIMER_IC, 100000);
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// Configure I/O APIC
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u32 *ioapic_reg=(u32*)ioapic_space;
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*ioapic_reg=0x12; // Select the 0x12 IRQ
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ioapic_reg=(u32*)(((u64)ioapic_space)+0x10); // Now use the IOREGWIN to write
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*ioapic_reg=(0x0<<12)|60; // Enable IRQ 1 (0x12) and assign it to the vector 0x3C (index 60 in the IDT)
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enable=1;
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}
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void apic_write(u32 reg, u32 value){
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u32 *lapic_reg=(u32*)(lapic_space+reg);
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*lapic_reg=value;
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}
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u32 apic_read(u32 reg){
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u32 *lapic_reg=(u32*)(lapic_space+reg);
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return *lapic_reg;
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}
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extern "C" void apic_ack(){
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if(enable){
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/* u8 data;
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do {
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inb(0x64,data);
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}
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while((data&0x01) == 0);
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inb(0x60,data); */
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apic_write(APIC_EOI, 0);
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}
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} |