loic/MicSim
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update readme

Browse source
This commit is contained in:
Loic GUEGAN 2018-08-31 20:10:48 +02:00
parent e0f3b5f394
commit ea840b6615
1 changed files with 7 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
README.md
View file

@ -16,4 +16,10 @@ All the architecture components are located in _components_ folder:
- **ram.py** Contains a simple RAM implementation - **ram.py** Contains a simple RAM implementation
### How to load code in memory ? ### How to load code in memory ?
Simply by editing **ram.txt**. Each line corresponding to a byte entry starting from address 0x0 to whatever to $+\infty$ . Each line can be an IJVM _opcode_ or a random byte. Simply by editing **ram.txt**. Each line corresponding to a byte entry starting from address 0x0 to whatever to $+\infty$ . Each line can be an IJVM _opcode_ or a random byte. Here is an example of how to add two number:
> BIPUSH
> 12
> BIPUSH
> 5
> IADD