From d58349763a312add267dbcaf53d0b9602b177d33 Mon Sep 17 00:00:00 2001
From: Loic GUEGAN <loic.guegan@yahoo.fr>
Date: Sat, 1 Sep 2018 16:49:12 +0200
Subject: [PATCH] Debug MBR register

---
 components/caretaker.py    | 12 ++++++------
 components/microprogram.py | 13 ++++++++++---
 micsim.py                  |  1 -
 ram.txt                    | 15 +++++----------
 4 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/components/caretaker.py b/components/caretaker.py
index 7f8cc33..4237702 100644
--- a/components/caretaker.py
+++ b/components/caretaker.py
@@ -11,12 +11,12 @@ class Caretaker:
 	
 	def __getitem__(self,key):
 		if key=="MBRU": # If we ask for unsigned
-			return(self.objects["MBR"] & 0x000000FF)
-		elif key=="MBR": # If we ask for signed
-			if self.objects["MBR"]>=0:
-				return(self["MBRU"])
-			else: # Send 2 complement if it's lower than 0
-				return(self.objects["MBR"] & 0xFFFFFFFF)
+			return(abs(self.objects["MBR"]))
+		elif key== "MBR":
+			if (self.objects[key]>>7)==1: # If it a negative number (2 complement)
+				return(-((self.objects[key]-1)^0xFF)) # transforme bin negative number to python negative number
+			else:
+				return(self.objects[key])
 		return(self.objects[key])
 
 	def __setitem__(self,key,value):# TODO: Do special treatment for MBR (allow only 2^8 value)
diff --git a/components/microprogram.py b/components/microprogram.py
index fb0e589..4543de1 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -45,7 +45,7 @@ class Microprogram:
 		"""
 			Execute next opcode
 		"""
-		opcode=self.c["MBR"] # Get loaded OpCode
+		opcode=self.c["MBRU"] # Get loaded OpCode (/!\ We used MBRU not MBR because MBR is signed)
 		if opcode==ijvm["NOP"]: # NOP
 			pass
 		elif opcode==ijvm["BIPUSH"]: # BIPUSH
@@ -135,16 +135,23 @@ class Microprogram:
 			self.c["H"]=self.c["MDR"]
 			self.c["MDR"]=self.c["MBR"]+self.c["H"]
 			self.wr()
+		elif opcode==ijvm["GOTO"]:
+			self.fetch();self.c["PC"]+=1 # Fetch first byte
+			self.c["OPC"]=self.c["PC"]-1
+			self.c["H"]=self.c["MBR"]<<8
+			self.fetch();self.c["PC"]+=1 # Fetch second byte
+			self.c["H"]=self.c["MBRU"]|self.c["H"]
+			self.c["PC"]=self.c["OPC"]+self.c["H"]
 		elif opcode==ijvm["OUT"]:
 			self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
-			print(str(chr(self.c["MBR"])),end="")
+			print(str(chr(self.c["MBRU"])),end="") # MBRU because no char which are negative
 		elif opcode==ijvm["HALT"]:
 			return(1)
 		else:
 			if opcode in ijvm:
 				print("Instruction {} not yet implemented.".format(ijvm[opcode]))
 			else:
-				raise RuntimeError("Instruction {} not found".format(opcode))
+				raise RuntimeError("Instruction {} not found on address {}".format(opcode,self.c["PC"]-1))
 		return(0)
 	
 	def dump(self):
diff --git a/micsim.py b/micsim.py
index 7cd14bd..46df648 100755
--- a/micsim.py
+++ b/micsim.py
@@ -13,4 +13,3 @@ c["RAM"]=RAM 					# Add ram to components
 mic=Microprogram(c) 			# Create micro program
 mic.run() 						# Run the micro program
 mic.dump() 						# Dump ram
-
diff --git a/ram.txt b/ram.txt
index 63af6dd..7132b9f 100644
--- a/ram.txt
+++ b/ram.txt
@@ -1,14 +1,9 @@
 BIPUSH
-4
+1
 BIPUSH
-5
-ILOAD
+0
+GOTO
+0
 0
 BIPUSH
-2
-IADD
-ISTORE
-1
-IINC
-1
-10
+3