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Debug test on ram

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This commit is contained in:
Loic GUEGAN 2018-09-02 18:46:31 +02:00
parent 1cc7b41a11
commit d0fc22d3e9
2 changed files with 26 additions and 14 deletions
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2
MicSim/components/ram.py
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@ -69,7 +69,7 @@ class Ram:
try: try:
value=self.data[addr] value=self.data[addr]
except: except:
if addr>self.lastAddr: if addr>self.lastAddr or addr<0:
raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr)) raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr))
if(value==None): if(value==None):
return(0) return(0)

38
MicSim/test/test_ram.py
View file

@ -11,6 +11,7 @@ class RamTest(unittest.TestCase):
Init test Init test
""" """
self.caretaker=dict({"MDR":0,"MAR":0,"MBR":0,"PC":0}) self.caretaker=dict({"MDR":0,"MAR":0,"MBR":0,"PC":0})
self.ramSize=1000*4 # Ram size should be a multiple of 4 to guaranty test validity
def test_write(self): def test_write(self):
""" """
@ -20,9 +21,9 @@ class RamTest(unittest.TestCase):
for i in range(0,32): # Test for n number for i in range(0,32): # Test for n number
toWrite=randint(0,2**i) # Pick a random number to write toWrite=randint(0,2**i) # Pick a random number to write
self.caretaker["MDR"]=toWrite self.caretaker["MDR"]=toWrite
self.caretaker["MAR"]=randint(0,10000-1) self.caretaker["MAR"]=randint(0,self.ramSize-1)
ram=Ram(self.caretaker,10000) ram=Ram(self.caretaker,self.ramSize)
ram.write() # Write a random number at address 0 ram.write() # Write a random number at address 0
data=ram.getData() # Dump ram data=ram.getData() # Dump ram
@ -47,13 +48,13 @@ class RamTest(unittest.TestCase):
""" """
Test read method Test read method
""" """
ram=Ram(self.caretaker,10000) ram=Ram(self.caretaker,self.ramSize)
data=dict() data=dict()
toWrite=randint(0,256-1) toWrite=randint(0,256-1)
for i in range(0,10000): # Write in memory for i in range(0,self.ramSize): # Write in memory
data[i]=toWrite # Write the random byte data[i]=toWrite # Write the random byte
ram.setData(data) ram.setData(data)
for i in range(0,int(10000/4)): # Read and check if its what we wrote for i in range(0,int(self.ramSize/4)): # Read and check if its what we wrote
self.caretaker["MAR"]=i*4 self.caretaker["MAR"]=i*4
data=ram.read() # Read start at 0 addr data=ram.read() # Read start at 0 addr
self.assertEqual(toWrite,(data>>24)&0xFF) self.assertEqual(toWrite,(data>>24)&0xFF)
@ -62,22 +63,33 @@ class RamTest(unittest.TestCase):
self.assertEqual(toWrite,data&0xFF) self.assertEqual(toWrite,data&0xFF)
# Try to read outside of the memory # Try to read outside of the memory
with self.assertRaises(Exception): with self.assertRaises(Exception):
self.caretaker["MAR"]=10000 self.caretaker["MAR"]=self.ramSize
ram.read() ram.read()
with self.assertRaises(Exception): with self.assertRaises(Exception):
self.caretaker["MAR"]=-10000 self.caretaker["MAR"]=-1*randint(0,self.ramSize-1)
ram.read() ram.read()
def test_fetch(self): def test_fetch(self):
""" """
Test fetch method Test fetch method
""" """
ram=Ram(self.caretaker,10000) # Test classical fetch
for i in range(1,10000): ram=Ram(self.caretaker,self.ramSize)
self.caretaker["MDR"]=i data=dict()
self.caretaker["MAR"]=i toWrite=randint(0,256-1)
ram.write() for i in range(0,self.ramSize):
data[i]=toWrite
ram.setData(data)
for i in range(0,self.ramSize):
self.caretaker["PC"]=i
self.assertEqual(toWrite,ram.fetch())
# Test fetch outside of memory
with self.assertRaises(Exception):
self.caretaker["PC"]=self.ramSize
ram.fetch()
with self.assertRaises(Exception):
self.caretaker["PC"]=-1*randint(0,self.ramSize-1)
ram.fetch()