diff --git a/components/caretaker.py b/components/caretaker.py
index ca15edd..f005b27 100644
--- a/components/caretaker.py
+++ b/components/caretaker.py
@@ -9,10 +9,11 @@ class Caretaker:
 			self.objects[reg]=0
 		self.objects["RAM"]=None
 	
-	def __getitem__(self,key):
+	def __getitem__(self,key): # TODO: Allow MBRU key and adapt its return value
 		return(self.objects[key])
 
-	def __setitem__(self,key,value):# TODO: Do special treatment for MBR
+	def __setitem__(self,key,value):# TODO: Do special treatment for MBR (allow only 2^8 value)
+									# TODO: Force data to be at most 32 bits longs (Mic-1 architecture constraint)
 		self.objects[key]=value
 		
 	def items(self):
diff --git a/components/ijvm.py b/components/ijvm.py
index 97fb6bd..86f5f63 100644
--- a/components/ijvm.py
+++ b/components/ijvm.py
@@ -1,4 +1,6 @@
 
+# Quick link about opcode: https://users-cs.au.dk/bouvin/dComArk/2015/noter/Note_2/#Instructions
+
 # Build IJVM
 ijvm=dict({
 	"BIPUSH":0x10,
diff --git a/components/microprogram.py b/components/microprogram.py
index 943e502..e1b81a0 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -41,7 +41,7 @@ class Microprogram:
 		"""
 		self.c["RAM"].write()
 
-	def exec(self):# link: https://users-cs.au.dk/bouvin/dComArk/2015/noter/Note_2/#Instructions
+	def exec(self): # TODO: Implement opcode
 		"""
 			Execute next opcode
 		"""
diff --git a/components/ram.py b/components/ram.py
index d503929..ddf48d1 100644
--- a/components/ram.py
+++ b/components/ram.py
@@ -8,6 +8,9 @@ class Ram:
 		self.c=components
 	
 	def loadRamFile(self,filepath):
+		"""
+			Load a Ram file into self.data
+		"""
 		data=dict()
 		addr=0
 		f=open(filepath,"r")
@@ -22,12 +25,18 @@ class Ram:
 		self.data=data
 	
 	def write(self):
+		"""
+			Write data to memory based Mic-1 architecture
+		"""
 		addr=self.c["MAR"]
 		if addr>self.lastAddr:
 			raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
 		self.data[addr]=self.c["MDR"]
 	
 	def read(self):
+		"""
+			Read data from memory based Mic-1 architecture
+		"""
 		addr=self.c["MAR"]
 		value=None
 		try:
@@ -40,6 +49,9 @@ class Ram:
 		return(value)
 		
 	def fetch(self):
+		"""
+			Fetch next byte from memory based Mic-1 architecture
+		"""
 		addr=self.c["PC"]
 		value=None
 		try:
@@ -52,11 +64,17 @@ class Ram:
 		return(value)
 		
 	def dump(self):
+		"""
+			Simple dump helper
+		"""
 		for key,value in self.data.items():
 			#print("{}:{}".format(key,bin(value)[2:]))
 			print("{}:{}".format(key,value))
 		
 	def dumpRange(self,start,end):
+		"""
+			Another dump helper
+		"""
 		for i in range(start,end+1):
 			try:
 				print("{}:{}".format(i,self.data[i]))