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Update RAM

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This commit is contained in:
Loic GUEGAN 2018-09-02 18:55:31 +02:00
parent d0fc22d3e9
commit 76d847cf01
2 changed files with 8 additions and 0 deletions
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2
MicSim/components/ram.py
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@ -37,6 +37,8 @@ class Ram:
addr=self.c["MAR"]
if addr>self.lastAddr or addr<0:
raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
if self.c["MDR"] >=2**32:
raise ValueError("You try to write a the value {} at address {} but this value does not fit in a int".format(self.c["MDR"],addr))
#### Split bytes and write ####
self.data[addr+3]=self.c["MDR"] & 0xFF
self.data[addr+2]=self.c["MDR"]>>8 & 0xFF

6
MicSim/test/test_ram.py
View file

@ -43,6 +43,12 @@ class RamTest(unittest.TestCase):
ram=Ram(self.caretaker,1000)
with self.assertRaises(Exception):
ram.write()
# Try to write that cannot fit in a int
self.caretaker["MDR"]=2**32
self.caretaker["MAR"]=0
ram=Ram(self.caretaker,1000)
with self.assertRaises(Exception):
ram.write()
def test_read(self):
"""