From 739548d99f3450b5def909f98ad65faa3509699a Mon Sep 17 00:00:00 2001
From: Loic GUEGAN <loic.guegan@yahoo.fr>
Date: Sat, 1 Sep 2018 10:19:06 +0200
Subject: [PATCH] Add opcodes

---
 components/caretaker.py    |  9 ++++++++-
 components/microprogram.py | 32 ++++++++++++++++++++++++++++++--
 micsim.py                  |  2 ++
 ram.txt                    | 13 ++++++++-----
 4 files changed, 48 insertions(+), 8 deletions(-)

diff --git a/components/caretaker.py b/components/caretaker.py
index f005b27..7f8cc33 100644
--- a/components/caretaker.py
+++ b/components/caretaker.py
@@ -9,7 +9,14 @@ class Caretaker:
 			self.objects[reg]=0
 		self.objects["RAM"]=None
 	
-	def __getitem__(self,key): # TODO: Allow MBRU key and adapt its return value
+	def __getitem__(self,key):
+		if key=="MBRU": # If we ask for unsigned
+			return(self.objects["MBR"] & 0x000000FF)
+		elif key=="MBR": # If we ask for signed
+			if self.objects["MBR"]>=0:
+				return(self["MBRU"])
+			else: # Send 2 complement if it's lower than 0
+				return(self.objects["MBR"] & 0xFFFFFFFF)
 		return(self.objects[key])
 
 	def __setitem__(self,key,value):# TODO: Do special treatment for MBR (allow only 2^8 value)
diff --git a/components/microprogram.py b/components/microprogram.py
index e1b81a0..fb0e589 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -86,7 +86,7 @@ class Microprogram:
 			self.c["MAR"]=self.c["SP"]
 			self.c["H"]=self.c["TOS"]
 			self.rd()
-			self.c["TOS"]=(self.c["MDR"] and self.c["H"])
+			self.c["TOS"]=(self.c["MDR"] & self.c["H"])
 			self.c["MDR"]=self.c["TOS"]
 			self.wr()
 		elif opcode==ijvm["IOR"]:
@@ -94,7 +94,7 @@ class Microprogram:
 			self.c["MAR"]=self.c["SP"]
 			self.c["H"]=self.c["TOS"]
 			self.rd()
-			self.c["TOS"]=(self.c["MDR"] or self.c["H"])
+			self.c["TOS"]=(self.c["MDR"] | self.c["H"])
 			self.c["MDR"]=self.c["TOS"]
 			self.wr()
 		elif opcode==ijvm["SWAP"]:
@@ -107,6 +107,34 @@ class Microprogram:
 			self.c["MAR"]=self.c["SP"]-1
 			self.wr()
 			self.c["TOS"]=self.c["H"]
+		elif opcode==ijvm["ILOAD"]:
+			self.fetch();self.c["PC"]+=1 # Fetch local variable  to push onto the stack
+			self.c["H"]=self.c["LV"]
+			self.c["MAR"]=self.c["MBRU"]+self.c["H"]
+			self.rd()
+			self.c["SP"]+=1
+			self.c["MAR"]=self.c["SP"]
+			self.wr()
+			self.c["TOS"]=self.c["MDR"]
+		elif opcode==ijvm["ISTORE"]:
+			self.fetch();self.c["PC"]+=1 # Fetch local variable offset where to store
+			self.c["H"]=self.c["LV"]
+			self.c["MAR"]=self.c["MBRU"]+self.c["H"]
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.rd()
+			self.c["TOS"]=self.c["MDR"]
+		elif opcode==ijvm["IINC"]:
+			self.fetch();self.c["PC"]+=1 # Fetch local variable offset to inc
+			self.c["H"]=self.c["LV"]
+			self.c["MAR"]=self.c["MBRU"]+self.c["H"]
+			self.rd()
+			self.fetch();self.c["PC"]+=1 # Fetch inc value
+			self.c["H"]=self.c["MDR"]
+			self.c["MDR"]=self.c["MBR"]+self.c["H"]
+			self.wr()
 		elif opcode==ijvm["OUT"]:
 			self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
 			print(str(chr(self.c["MBR"])),end="")
diff --git a/micsim.py b/micsim.py
index 1e4db48..d85f2b9 100755
--- a/micsim.py
+++ b/micsim.py
@@ -14,4 +14,6 @@ mic=Microprogram(c) 			# Create micro program
 mic.run() 						# Run the micro program
 mic.dump() 						# Dump ram
 
+c["MBR"]=-1
+print(c["MBR"])
 
diff --git a/ram.txt b/ram.txt
index f86ca50..63af6dd 100644
--- a/ram.txt
+++ b/ram.txt
@@ -1,11 +1,14 @@
 BIPUSH
+4
+BIPUSH
 5
+ILOAD
+0
 BIPUSH
 2
 IADD
-BIPUSH
+ISTORE
+1
+IINC
+1
 10
-POP
-HALT
-OUT
-65