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Loic GUEGAN 2018-09-02 18:31:11 +02:00
parent 80e4c1d603
commit 1cc7b41a11
4 changed files with 82 additions and 17 deletions
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4
MicSim/components/microprogram.py
View file

@ -32,7 +32,9 @@ class Microprogram:
"""
Read data into memory
"""
self.c["MAR"]=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
little_endian=self.c["RAM"].read()
self.c["MAR"]=self.c["MAR"]/4 # Restore MAR
##### Build little endian version of MDR ####
big_endian=(little_endian&0xFF)<<24
big_endian=big_endian|(((little_endian>>8)&0xFF)<<16)
@ -53,7 +55,9 @@ class Microprogram:
##############################################
big_endian=self.c["MDR"] # Backup MDR before change it to little endian
self.c["MDR"]=little_endian # Load little endian value
self.c["MAR"]=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
self.c["RAM"].write() # Write little endian value into memory
self.c["MAR"]=self.c["MAR"]/4 # Restore MAR
self.c["MDR"]=big_endian # Restore big endian
def exec(self): # TODO: Implement opcode

18
MicSim/components/ram.py
View file

@ -34,8 +34,8 @@ class Ram:
"""
Write data to memory based Mic-1 architecture
"""
addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
if addr>self.lastAddr:
addr=self.c["MAR"]
if addr>self.lastAddr or addr<0:
raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
#### Split bytes and write ####
self.data[addr+3]=self.c["MDR"] & 0xFF
@ -48,13 +48,13 @@ class Ram:
"""
Read data from memory based Mic-1 architecture
"""
addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
addr=self.c["MAR"]
value=None
try:
#### Combine bytes ####
value=self.data[addr]<<24|(self.data[addr+1]<<16)|(self.data[addr+2]<<8)|(self.data[addr+3])
except:
if addr>self.lastAddr:
if addr>self.lastAddr or addr<0:
raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr))
if(value==None):
return(0)
@ -75,9 +75,15 @@ class Ram:
return(0)
return(value)
def dump(self):
def getData(self):
"""
Fetch RAM data (usefull for unit tests)
Get RAM data (usefull for unit tests)
"""
return(self.data)
def setData(self,data):
"""
Set RAM data (usefull for unit tests)
"""
self.data=data

3
MicSim/ram.txt
View file

@ -1,2 +1,5 @@
BIPUSH
9
BIPUSH
8
IADD

72
MicSim/test/test_ram.py
View file

@ -16,17 +16,69 @@ class RamTest(unittest.TestCase):
"""
Test write method
"""
toWrite=randint(0,2**32) # Pick a random number to write
self.caretaker["MDR"]=toWrite
ram=Ram(self.caretaker,10000)
ram.write() # Write a random number at address 0
# Test write action
for i in range(0,32): # Test for n number
toWrite=randint(0,2**i) # Pick a random number to write
self.caretaker["MDR"]=toWrite
self.caretaker["MAR"]=randint(0,10000-1)
ram=Ram(self.caretaker,10000)
ram.write() # Write a random number at address 0
data=ram.getData() # Dump ram
##### Test if everything is written using big endian model #####
self.assertEqual((toWrite>>24)&0xFF,data[self.caretaker["MAR"]])
self.assertEqual((toWrite>>16)&0xFF,data[self.caretaker["MAR"]+1])
self.assertEqual((toWrite>>8)&0xFF,data[self.caretaker["MAR"]+2])
self.assertEqual(toWrite&0xFF,data[self.caretaker["MAR"]+3])
# Test error is raise when writing out of memory
self.caretaker["MDR"]=randint(0,2**i)
self.caretaker["MAR"]=1000 # Write out of memory (positive address)
ram=Ram(self.caretaker,1000)
with self.assertRaises(Exception):
ram.write()
self.caretaker["MDR"]=randint(0,2**i)
self.caretaker["MAR"]=-1000 # Write out of memory (negative address)
ram=Ram(self.caretaker,1000)
with self.assertRaises(Exception):
ram.write()
def test_read(self):
"""
Test read method
"""
ram=Ram(self.caretaker,10000)
data=dict()
toWrite=randint(0,256-1)
for i in range(0,10000): # Write in memory
data[i]=toWrite # Write the random byte
ram.setData(data)
for i in range(0,int(10000/4)): # Read and check if its what we wrote
self.caretaker["MAR"]=i*4
data=ram.read() # Read start at 0 addr
self.assertEqual(toWrite,(data>>24)&0xFF)
self.assertEqual(toWrite,(data>>16)&0xFF)
self.assertEqual(toWrite,(data>>8)&0xFF)
self.assertEqual(toWrite,data&0xFF)
# Try to read outside of the memory
with self.assertRaises(Exception):
self.caretaker["MAR"]=10000
ram.read()
with self.assertRaises(Exception):
self.caretaker["MAR"]=-10000
ram.read()
def test_fetch(self):
"""
Test fetch method
"""
ram=Ram(self.caretaker,10000)
for i in range(1,10000):
self.caretaker["MDR"]=i
self.caretaker["MAR"]=i
ram.write()
data=ram.dump() # Dump ram
##### Test if everything is written using big endian model #####
self.assertEqual((toWrite>>24)&0xFF,data[self.caretaker["MAR"]])
self.assertEqual((toWrite>>16)&0xFF,data[self.caretaker["MAR"]+1])
self.assertEqual((toWrite>>8)&0xFF,data[self.caretaker["MAR"]+2])
self.assertEqual(toWrite&0xFF,data[self.caretaker["MAR"]+3])